1. Field of the Invention
The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device and a method for fabricating the same, configured to prevent a “smiling” phenomenon in an ONO (oxide-nitride-oxide) layer in a SONOS nonvolatile memory device.
2. Discussion of the Related Art
Generally, nonvolatile memory devices are advantageous in that data is not lost even when a power supply is stopped. In this respect, nonvolatile memory devices are widely used for data storage of a PC BIOS, a set-top box, a printer or a network server. Recently, nonvolatile memory devices are also used for a digital camera and a mobile phone.
Among nonvolatile memory devices, an EEPROM (Electrically Erasable Programmable Read-Only Memory) type nonvolatile memory device may completely erase data from memory cells, or may erase data from memory cells by each unit sector. In this EEPROM type nonvolatile memory device, in a programming mode, channel hot electrons are generated at the side of the drain and stored in a floating gate, whereby a threshold voltage of a cell transistor increases. In an erasing mode of the EEPROM type nonvolatile memory device, a relatively high voltage is generated between the floating gate and source/substrate, and the electrons stored in the floating gate are discharged, thereby lowering the threshold voltage of the cell transistor.
With rapid development of high-integration devices, the size of the floating gate type cell has generally decreased according to the related art. However, beyond a certain size, it is difficult to decrease the cell size further since the cell generally requires a relatively high voltage in the programming and erasing modes. Furthermore, it is difficult to obtain sufficient process margin for defining tunneling. For these (and other) reasons, various nonvolatile memory devices such as SONOS, FeRAM, SET and NROM have been studied actively as a substitute for the floating gate type cell. Among them, the SONOS cell has attracted great attention as a substitute nonvolatile memory device for the floating gate type cell.
In the meantime, the EEPROM type nonvolatile memory device may have an ETOX cell or a split gate type cell. The ETOX cell is formed in a simple stack structure. In case of the split gate type cell, two transistors are formed in each cell. Specifically, the ETOX cell has the stack structure of a floating gate and a control gate, wherein the floating gate stores charges therein, and the control gate receives a power. Meanwhile, in case of the split gate type cell, one memory cell includes the two transistors; that is, a selection transistor for selecting the cell, and a memory transistor for storing data. The memory transistor includes a floating gate, a control gate electrode, and a gate interlayer dielectric, wherein the floating gate stores charges therein, the control gate electrode controls the memory transistor, and the gate interlayer dielectric is interposed between the floating gate and the control gate electrode.
Hereinafter, a related art split gate type SONOS structure nonvolatile memory device will be described as follows.
FIG. 1 is a cross sectional view of a split gate type SONOS structure nonvolatile memory device according to the related art. FIG. 2A to FIG. 2F are cross sectional views of the process for fabricating a split gate type SONOS structure nonvolatile memory device according to the related art.
As shown in FIG. 1, a gate stack 17 is formed on a predetermined portion of a semiconductor substrate 11, wherein the gate stack 17 has a structure of a sequentially stacked ONO layer (tunnel oxide 12a-trap nitride 12b-block oxide 12c) 12, control gate 13a, CVD (chemical vapor deposition layer 18 is formed at both sides of the stack gate 17 on the surface of the semiconductor substrate 11.
Also, a selection gate 19a partially overlaps with the gate stack 17. An oxide layer 16 is formed at both sides of the control gate 13a, whereby the selection gate 19a is insulated from the control gate 13a. 
At this time, one side of the selection gate 19a overlaps with the gate stack 17, and the other side of the selection gate 19a overlaps with the semiconductor substrate 11. Also, the selection gate 19a is insulated from the semiconductor substrate 11 by the gate oxide layer 18.
Then, source and drain regions 20 and 21 are formed at both sides of the selection gate 19a and the gate stack 17 in the semiconductor substrate 11. Also, the selection gate 19a, the control gate 13a, the source region 20 and the drain region 21 are connected with respective lines for applying a bias voltage for programming, erasing and reading operations.
A method for fabricating the split gate type SONOS cell according to the related art will be described as follows.
First, as shown in FIG. 2A, the tunnel oxide layer 12a, the trap nitride layer 12b and the block oxide layer 12c are sequentially stacked on the semiconductor substrate 11, thereby forming the ONO layer 12. Then, a first polysilicon layer 13, the CVD oxide layer 14 and the nitride layer 15 are sequentially formed on the ONO layer 12.
As shown in FIG. 2B, the first polysilicon layer 13, the CVD oxide layer 14 and the nitride layer 15 are selectively etched to remain on the predetermined portion of the semiconductor substrate 11. At this time, the etched first polysilicon layer 13 serves as the control gate 13a. By oxidizing the exposed portion of the control gate 13a, the oxide layer 16 is formed at the sides of the control gate 13a. 
As shown in FIG. 2C, the ONO layer 12 is removed using the etched nitride layer 15 as a mask. Accordingly, it is possible to form the gate stack 17 including the ONO layer 12, the control gate 13a, the CVD oxide layer 14 and the nitride layer 15.
Referring to FIG. 2D, the gate oxide layer 18 is formed at both sides of the stack gate 18 in the surface of the semiconductor substrate 11 by oxidizing the surface of the exposed semiconductor substrate 11. Then, a second polysilicon layer 19 is formed on the entire surface of the semiconductor substrate 11 including the gate stack 17.
At this time, when forming the gate oxide layer 18, as shown in the drawings, the edge of the control gate 13a of the polysilicon material may be oxidized, thereby generating a “smiling” phenomenon in the ONO layer 12.
As shown in FIG. 2E, the second polysilicon layer 19 is selectively etched to remain on the predetermined portion of the gate stack 17 and the semiconductor substrate 11, thereby forming the selection gate 19a. Then, impurity ions are implanted into the semiconductor substrate 11 using the selection gate 19a and the gate stack 17 as a mask, thereby forming the source region 20 and the drain region 21. At this time, the source region 20 is formed at one side of the selection gate 19a in the semiconductor substrate 11, and the drain region 21 is formed at the opposite side of the gate stack 17 in the semiconductor substrate 11.
After that, as shown in FIG. 2F, conductive lines are respectively formed to the selection gate 19a, the control gate 13a, and the source and drain regions 20 and 21. Accordingly, it is possible to complete the split gate type SONOS cell.
However, the split gate type SONOS nonvolatile memory device according to the related art has the following disadvantages.
In the split gate type SONOS nonvolatile memory device according to the related art, when oxidizing the semiconductor substrate to form the gate oxide layer 18, the corner(s) of the control gate 13a may be oxidized, thereby generating the “smiling” phenomenon in the ONO layer. Also, the hot carriers generated during programming may tunnel or permeate into the portion of the ONO layer having the smiling phenomenon. In this case, it is difficult to perform the erasing operation. That is, when applying an erasing voltage, an electric field may not completely remove all charge carriers from the ONO layer, so that it becomes difficult to improve efficiency in the erasing operation.